Impact of Gate Line-Edge Roughness (LER) Versus Random Dopant Fluctuations (RDF) on Germanium-Source Tunnel FET Performance

Author

Damrongplasit, Nattapol ; Sung Hwan Kim ; Changhwan Shin ; Liu, T.-J King

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, Berkeley, CA, USA

Volume

12

Issue

6

fYear

2013

fDate

Nov. 2013

Firstpage

1061

Lastpage

1067

Abstract

The impact of gate line-edge roughness (LER) on the performance of the planar germanium-source tunnel FET with gate length Lg = 30 nm is studied via 3-D device simulation. Depending on the source formation process, gate LER can result in source LER. Therefore, two extreme cases of the source edge profile are considered herein: smooth edge and rough edge. Threshold voltage VT variation due to gate LER is found to be minimal in each case, as compared to VT variation caused by random dopant fluctuations (RDF). Gate LER is also found to have negligible impact on the off-state leakage current floor. In the case of a source with smooth edge, gate-LER induced variation in on-state drive current can be significant.

Keywords

elemental semiconductors; field effect transistors; germanium; leakage currents; tunnel transistors; 3D device simulation; Ge; RDF; gate LER; gate line-edge roughness; off-state leakage current floor; on-state drive current; planar germanium-source tunnel FET performance; random dopant fluctuation; rough edge profile; size 30 nm; smooth edge profile; source LER; source edge profile; source formation process; Doping; Logic gates; Resource description framework; Silicon; Solid modeling; Threshold voltage; Tunneling; Line-edge roughness (LER); TFET; TFET variability; random dopant fluctuation (RDF); tunneling; variability; vertical tunneling;

fLanguage

English

Journal_Title

Nanotechnology, IEEE Transactions on

Publisher

ieee

ISSN

1536-125X

Type

jour

DOI

10.1109/TNANO.2013.2278153

Filename

6578555