Design and FPGA Implementation of High-Speed, Fixed-Latency Serial Transceivers

Fixed-latency serial links are important components of the distributed measurement and control systems. However, most high-speed Serializer-Deserializer (SerDes) chips do not keep the same link latency after each power-up or reset. In this paper, we propose a fixed-latency serial transceiver based on dynamic clock phase shifting and changeable delay tuning technologies. Our solution can process all possible phase offsets between the transmitted and received clocks, so it relaxes the requirement of fanning in the same reference clock both to the transmitter and to the receiver. It also eliminates the reset-relock process in the roulette approach. We present a specific example of implementation based on the serial transceiver in Xilinx Virtex 5 FPGA. The experiment results indicate that our transceiver can achieve a deterministic latency with sub-nanosecond precision.