MOSFET optimization in deep submicron technology for charge amplifiers

Author

De Geronimo, Gianluigi ; O´Connor, Paul

Author_Institution

Instrum. Div., Brookhaven Nat. Lab., Upton, NY

Volume

52

Issue

6

fYear

2005

Firstpage

3223

Lastpage

3232

Abstract

The optimization of the input MOSFET for charge amplifiers in deep submicron technologies is discussed. After a review of the traditional approach, the impact of properly modeling the equivalent series noise and gate capacitance of the MOSFET is presented. It is shown that the enhanced MOSFET model, when compared to the classical, produces a different resolution estimate and input MOSFET optimization result. The minimum channel length and the maximum allocated power are not always the best choice in terms of resolution. Also, in an optimized front-end, the low frequency noise contribution to the Equivalent Noise Charge may depend on the time constant of the filter. As an example, results from the commercial TSMC 0.25 mum CMOS technology are reported

Keywords

CMOS integrated circuits; MOSFET; amplifiers; nuclear electronics; optimisation; semiconductor device models; semiconductor device noise; channel length; charge amplifiers; commercial TSMC CMOS technology; deep submicron technology; enhanced MOSFET optimization; equivalent noise charge; filter; frequency noise; gate capacitance; optimized front-end electronics; CMOS technology; Capacitance; Circuit noise; Design optimization; Filters; Low-frequency noise; MOSFET circuits; Semiconductor device modeling; Sensor phenomena and characterization; Signal resolution; CMOS; Charge amplifier; MOSFET;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2005.862938

Filename

1589350