• DocumentCode
    821548
  • Title

    Synaptic plasticity in spiking neural networks (SP2INN): a system approach

  • Author

    Mehrtash, Nasser ; Jung, Dietmar ; Hellmich, Heik Heinrich ; Schoenauer, Tim ; Lu, Vi Thanh ; Klar, Heinrich

  • Author_Institution
    Dept. of Comput. Sci. & Electr. Eng., Tech. Univ. of Berlin, Germany
  • Volume
    14
  • Issue
    5
  • fYear
    2003
  • Firstpage
    980
  • Lastpage
    992
  • Abstract
    In this paper, we present a digital system called (SP2INN) for simulating very large-scale spiking neural networks (VLSNNs) comprising, e.g., 1000000 neurons with several million connections in total. SP2INN makes it possible to simulate VLSNN with features such as synaptic short term plasticity, long term plasticity as well as configurable connections. For such VLSNN the computation of the connectivity including the synapses is the main challenging task besides computing the neuron model. We describe the configurable neuron model of SP2INN, before we focus on the computation of the connectivity. Within SP2INN, connectivity parameters are stored in an external memory, while the actual connections are computed online based on defined connectivity rules. The communication between the SP2INN processor and the external memory represents a bottle-neck for the system performance. We show this problem is handled efficiently by introducing a tag scheme and a target-oriented addressing method. The SP2INN processor is described in a high-level hardware description language. We present its implementation in a 0.35 μm CMOS technology, but also discuss advantages and drawbacks of implementing it on a field programmable gate array.
  • Keywords
    CMOS integrated circuits; field programmable gate arrays; neural nets; 0.35 micron; CMOS technology; FPGA; SP2INN; VLSNN; bottle-neck; configurable connections; connectivity; digital system; field programmable gate array; hardware description language; large-scale spiking neural network simulation; long-term plasticity; synaptic plasticity; synaptic short-term plasticity; system approach; tag scheme; target-oriented addressing method; Application specific integrated circuits; Artificial neural networks; CMOS technology; Computational modeling; Field programmable gate arrays; Hardware design languages; Intelligent networks; Large-scale systems; Neural networks; Neurons;
  • fLanguage
    English
  • Journal_Title
    Neural Networks, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1045-9227
  • Type

    jour

  • DOI
    10.1109/TNN.2003.816060
  • Filename
    1243704