DocumentCode
821749
Title
Analog soft-pattern-matching classifier using floating-gate MOS technology
Author
Yamasaki, Toshihiko ; Shibata, Tadashi
Author_Institution
Dept. of Electron. Eng., Univ. of Tokyo, Japan
Volume
14
Issue
5
fYear
2003
Firstpage
1257
Lastpage
1265
Abstract
A flexible analog pattern-matching classifier has been developed and its performance is demonstrated in conjunction with a robust image representation algorithm called projected principal-edge distribution (PPED). In the circuit, the functional form of matching is made tunable in terms of the peak position, the peak height and the sharpness of the similarity evaluation by employing the floating-gate MOS technology. The test chip was fabricated in a 0.6-μm complimentary metal-oxide semiconductor technology and successfully applied to the recognition of simple handwritten patterns and Arabic numerals using the PPED algorithm for robust image coding. The separation and classification of overlapping patterns have been also experimentally demonstrated.
Keywords
MOS logic circuits; VLSI; handwritten character recognition; image coding; image representation; neural chips; pattern classification; pattern matching; Arabic numerals; analog soft-pattern-matching classifier; experiment; flexible analog pattern-matching classifier; floating-gate MOS technology; handwritten pattern recognition; image coding; metal-oxide semiconductor technology; neural nets; performance; projected principal-edge distribution; robust image representation; template matching; Circuit testing; Handwriting recognition; Image coding; Image recognition; Image representation; MOS devices; Pattern recognition; Robustness; Semiconductor device testing; Tunable circuits and devices;
fLanguage
English
Journal_Title
Neural Networks, IEEE Transactions on
Publisher
ieee
ISSN
1045-9227
Type
jour
DOI
10.1109/TNN.2003.816031
Filename
1243725
Link To Document