Title :
Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation
Author :
Leblebici, Yusuf ; Kang, Sung-Mo
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
fDate :
2/1/1992 12:00:00 AM
Abstract :
The authors present an accurate one-dimensional device model for the simulation of nMOS transistors with hot-carrier-induced oxide damage. The model uses a realistic charge density distribution profile to account for the localization of the oxide-interface charge near the drain. Model simulation results obtained for nMOS transistors with hot-carrier-induced oxide damage demonstrate good agreement with the experimental data. The amount and the location of the hot-carrier-induced oxide damage are simulated by using only a few parameters, which simplifies the implementation of the model in a reliability simulation environment. The proposed model has been implemented in the iSMILE circuit simulator, and the capabilities of the model have been explored by various circuit simulation examples. The damaged-MOSFET model presented offers a simple and accurate approach for simulating the circuit behavior after hot-carrier damage
Keywords :
digital simulation; electronic engineering computing; hot carriers; insulated gate field effect transistors; semiconductor device models; NMOS transistors; charge density distribution profile; circuit degradation; circuit simulator; damaged-MOSFET model; device degradation; hot carrier degradation; hot-carrier-induced oxide damage; iSMILE; n-channel MOSFET; one-dimensional device model; oxide-interface charge; simulation; Aging; Circuit optimization; Circuit simulation; Circuit testing; Computational modeling; Degradation; Hot carriers; Integrated circuit reliability; MOSFETs; Very large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on