Analysis and design of latch-controlled synchronous digital circuits

The authors present a succinct formulation of the timing constraints for latch-controlled synchronous digital circuits. It is shown that the constraints are mildly nonlinear. The equivalence of the nonlinear optimal cycle time calculation problem to an associated and simpler linear programming (LP) problem is proved. A LP-based algorithm which is guaranteed to obtain the optimal cycle time for arbitrary circuits controlled by a general class of multiphase overlapped clocks is presented. The formulation and an initial implementation of the algorithm on some example circuits are illustrated