DocumentCode
8235
Title
Interconnection system for the spiNNaker biologically inspired multi-computer
Author
Dugan, Kathryn ; Reeve, Jeff ; Brown, Andrew ; Furber, Steve
Author_Institution
Sch. of Electron. & Comput. Sci., Univ. of Southampton, Southampton, UK
Volume
7
Issue
3
fYear
2013
fDate
May-13
Firstpage
115
Lastpage
121
Abstract
SpiNNaker is a large-scale multi-core computing engine designed to model heavily distributed fine-grain problems. The machine is constructed hierarchically: 1 monitor and 16 worker processors form a single node of a toroidal compute `surface´. The six high-speed bi-directional links of each node are used for triangular edge connections that provide alternative routes around problematic links. The system itself is scalable from one node up to 216 resulting in a maximum of 220 worker processors. SpiNNaker is an isotropic homogeneous network of processors that deliberately includes no central overseer. A consequence of this isotropy is an absence of perimeter and hence no natural position for peripheral I/O connections. This study describes the practical techniques and details employed in two components of the system: (a) SpiNNlink is the proposed board-to-board interconnection system that multiplexes 48 separate 250 Mbps SpiNNaker links through six off-board connections without compromising the overall system bisection bandwidth, forms an isotropic meta-network on top of SpiNNaker without requiring any cooperation from system software, and remains transparent to the SpiNNaker network; and (b) SpiNNterceptor is the proposed peripheral I/O subsystem developed as a layer on top of SpiNNlink that provides over 18 Gbps of minimally disruptive communication between SpiNNaker applications and externally connected equipment.
Keywords
multiprocessing systems; multiprocessor interconnection networks; SpiNNaker biologically inspired multicomputer; board-to-board interconnection system; fine-grain problem; interconnection system; isotropic homogeneous processor network; isotropic meta-network; monitor processor; multicore computing engine; peripheral input-output connection; system bisection bandwidth; toroidal compute surface; triangular edge connection; worker processor;
fLanguage
English
Journal_Title
Computers & Digital Techniques, IET
Publisher
iet
ISSN
1751-8601
Type
jour
DOI
10.1049/iet-cdt.2012.0139
Filename
6547083
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