Simulated performance of analog Viterbi detectors

The reasons for pursuing analog implementations of the Viterbi algorithm for detection are presented. Some of the tradeoffs to be considered in choosing an analog architecture are discussed, and a suitable architecture for investigation is given. Simulation results based on the chosen architecture are presented and clearly show that analog implementations of the maximum likelihood sequence detector are worth pursuing. In addition, the simulation results provide quantitative guidelines for establishing the required specifications of the individual circuit blocks required to construct a Viterbi detector