A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques

Author

Keunsoo Song ; Sangkwon Lee ; Dongkyun Kim ; Youngbo Shim ; Sangil Park ; Bokrim Ko ; Duckhwa Hong ; Yongsuk Joo ; Wooyoung Lee ; Yongdeok Cho ; Wooyeol Shin ; Jaewoong Yun ; Hyengouk Lee ; Jeonghun Lee ; Eunryeong Lee ; Namkyu Jang ; Jaemo Yang ; Hae-kan

Author_Institution

SK hynix, Icheon, South Korea

Volume

50

Issue

8

fYear

2015

fDate

Aug. 2015

Firstpage

1945

Lastpage

1959

Abstract

The demands on higher bandwidth with reduced power consumption in mobile market are driving mobile DRAM with advanced design techniques. Proposed LPDDR4 in this paper achieves over 39% improvement in power efficiency and over 4.3 Gbps data rate with 1.1 V supply voltage. These are challenging targets compared with those of LPDDR3. This work describes design schemes employed in LPDDR4 to satisfy these requirements, such as multi-channel-per-die architecture, multiple training modes, low-swing interface, DQS and clock frequency dividing, and internal reference for data and command-address signals. This chip was fabricated in a 3-metal 2y-nm DRAM CMOS process.

Keywords

CMOS memory circuits; DRAM chips; mobile handsets; CMOS process; DQS; LPDDR4 mobile device; bandwidth improvement techniques; clock frequency dividing; command address signal reference; data signal reference; internal reference; low swing interface; mobile DRAM; multichannel-per-die architecture; multiple training modes; voltage 1.1 V; Bandwidth; Clocks; Mobile communication; Oscillators; Random access memory; Timing; Training; Command bus training; DQS oscillator; DRAM; LPDDR4; ZQ calibration; dram interface; memory SERDES; memory architecture; read DQ calibration; tDQS2DQ; training; write leveling; write training;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2015.2429588

Filename

7115193