The single chip versus multichip packaging option for digital CMOS in the 1990s

Author

Neugebauer, Constantine A. ; Fillion, Raymond A. ; Daum, Wolfgang ; Gdula, Michael

Author_Institution

GE Corporate Res. & Dev., Schenectady, NY, USA

Volume

15

Issue

5

fYear

1992

fDate

10/1/1992 12:00:00 AM

Firstpage

915

Lastpage

922

Abstract

The level of functional density achievable in digital CMOS logic chips is so high that in the past systems implementations by multichip module (MCM) packaging appear to have been unnecessary, because the system was usually made up of only a few chips. However, rapidly increasing system sizes anticipated in the future will require many VLSI/ULSI CMOS chips per system, operating at near 100 MHz clock frequency. The authors have, therefore, reexamined the single-chip versus MCM packaging option for digital CMOS for the 1990s. They conclude that, for large-scale CMOS logic systems constructed by the use of many state-of-the-art VLSI/ULSI chips, the MCM packaging approach gives a manyfold improvement in packing density (3-8×), performance (up to 1.4×), and cost (1.2×) over the SCM packaging approach

Keywords

CMOS integrated circuits; VLSI; design engineering; digital circuits; multichip modules; packaging; 100 MHz; MCM packaging option; SCM packaging approach; ULSI; VLSI; clock frequency; cost; digital CMOS; functional density; large-scale CMOS logic systems; multichip module; packing density; performance; single chip module packaging; CMOS logic circuits; CMOS technology; Chip scale packaging; Clocks; Costs; Microprocessor chips; Multichip modules; Senior members; Ultra large scale integration; Very large scale integration;

fLanguage

English

Journal_Title

Components, Hybrids, and Manufacturing Technology, IEEE Transactions on

Publisher

ieee

ISSN

0148-6411

Type

jour

DOI

10.1109/33.180058

Filename

180058