Compact on-chip measurement system for testing programmable delay lines

A compact on-chip measurement system is proposed for the testing of multiple programmable delay lines (timing digital-to-analogue converters (DACs)) through a low-speed analogue test bus. The system consists of very small delay-to-current converters local to each timing DAC, multiplexed to a centrally located programmable-gain sense amplifier. Silicon test results demonstrate that the system is capable of characterising the delay against the control code relationship of a timing DAC.