Design Exploration With Imprecise Latency and Register Constraints

This paper proposes a design exploration framework that considers impreciseness in design specification. In high-level synthesis, imprecise information is often encountered. Two types of impreciseness are considered, namely: 1) impreciseness underlying on functional unit specifications and 2) impreciseness due to system constraints, i.e., latency and register constraints. The framework is iterative and based on a core scheduling called "register-constrained inclusion scheduling." An example of how the scheduling algorithm works is shown. The effectiveness of the proposed framework for imprecise specification is demonstrated by exploring a design solution for three well-known benchmarks, namely: 1) discrete cosine transform; 2) Voltera filter; and 3) fast Fourier transform. The selected solution meets the acceptability criteria while minimizing the total number of registers