Modeling of distributed parasitics in power FETs

A distributed circuit analysis of power FETs accounting for the lateral source parasitic impedance in addition to the lateral drain and gate parasitic impedances is presented. Both a numerical solution and an exact analytic solution are derived. Using the exact analytic solution, approximate equivalent circuits are derived for FETs of short gate width for two common types of boundary conditions. When the gate and drain terminals are located on opposite sides of the distributed FET, the lateral source parasitic impedance can be represented for short gate width FETs by an equivalent circuit with a negative series impedance in series with the source terminal. The practical consequences on parameter extraction for device modeling are discussed. The availability of an exact analytic solution for the distributed FET should also assist with the synthesis of traveling wave FETs.