Low-cost software-based self-testing of RISC processor cores

Software self-testing of embedded processor cores, which effectively partitions the testing effort between low-speed external equipment and internal processor resources, has been recently proposed as an alternative to classical hardware built-in self-test techniques over which it provides significant advantages. A low-cost software-based self-testing methodology for processor cores is presented with the aim of producing compact test code sequences developed with a limited engineering effort and achieving a high fault coverage for the processor core. The objective of small test code sequences is directly related to the utilisation of low-speed external testers, since test time is primarily determined by the time required to download the test code to the processor memory at the tester´s low frequency. Successful application of the methodology to an RISC processor core architecture with a three-stage pipeline is demonstrated