Experimental characterization of the diode-type polysilicon loads for CMOS SRAM

Author

Kalnitsky, Alexander ; Li, Jia ; Chen, C. E Daniel

Author_Institution

SGS-Thomson Microelectronics, Inc., Carrollton, TX, USA

Volume

40

Issue

2

fYear

1993

fDate

2/1/1993 12:00:00 AM

Firstpage

358

Lastpage

363

Abstract

Experimental characterization of the diode-type n⁺-p-n ⁺ poly-Si loads for SRAM applications demonstrates that the resistance of the structure and its response to the bit-line voltages are dominated by such properties of the parasitic thin-film transistor associated with this device as fixed positive charge and `gate´ oxide thickness. Topographical effects observed in this study are interpreted in terms of the thickness variation of a dielectric overlaying the poly-Si feature and the fixed positive charges present in this dielectric in the vicinity of the poly-Si surface

Keywords

CMOS integrated circuits; SRAM chips; contact resistance; integrated circuit testing; interface electron states; rapid thermal processing; scanning electron microscopy; CMOS SRAM; RTA; SEM; Si-SiO₂; SiO₂-Si₃N₄ interface; bit-line voltages; dielectric thickness variation; diode-type polysilicon loads; fixed positive charge; gate oxide thickness; n⁺-p-n⁺ structure resistance; parasitic thin-film transistor; topographical effects; Contacts; Dielectrics; Diodes; Doping; Fabrication; Hydrogen; Manufacturing; Random access memory; Resistors; Surface resistance;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.182514

Filename

182514