A novel trench planarization technique using polysilicon refill, polysilicon oxidation, and oxide etchback

Planarization of polysilicon trench refill by the method of sequential oxidation and oxide etchback is reported. It is shown to result in an excellent wafer surface topography and improved wafer yield compared to the conventional planarization process that utilizes a blanket reactive ion etch removal of the refill. Trench capacitors with varying aspect ratios were fabricated and tested for gate yield, MOS interface characteristics, and gate oxide reliability. The measured MOS interface properties were excellent for trench capacitors planarized using the technique. The wafer yield was in excess of 90%, as compared to less than 65% for the conventional process. The uniformity of the planarization process across 4-in-diameter silicon wafers was also significantly improved. These results demonstrate that the process is attractive for fabricating high-density trench MOS structures in a manufacturing environment