Title :
High-Performance p-Channel LDMOS Transistors and Wide-Range Voltage Platform Technology Using Novel p-Channel Structure
Author :
Shimamoto, Satoshi ; Yanagida, Yohei ; Shirakawa, Shinji ; Miyakoshi, Kenji ; Oshima, Takayuki ; Sakano, Junichi ; Wada, Shinichiro ; Noguchi, Junji
Author_Institution :
Micro Device Div., Hitachi, Ltd., Ome, Japan
Abstract :
High-performance p-channel lateral double-diffused MOS (LDMOS) transistors designed to operate in a wide voltage range from 35 to 200 V and built using silicon-on-insulator LDMOS platform technology were studied. A novel channel structure was applied, and consequently, a high saturation drain current of 172 μA/μm in the 200-V p-channel LDMOS transistor was achieved, which is comparable to that of an n-channel LDMOS transistor. A low on -resistance of 3470 mΩ·mm2 was obtained while maintaining high on- and off-state breakdown voltages of -240 and -284 V. The 35-200-V LDMOS transistors with low on-resistance were also demonstrated by optimizing the layout, i.e., the reduced surface field structure and field plates.
Keywords :
MOSFET; semiconductor device breakdown; silicon-on-insulator; channel structure; field plates; high-performance p-channel LDMOS transistor; high-performance p-channel lateral double-diffused MOS transistor; n-channel LDMOS transistor; off-state breakdown voltage; on-state breakdown voltage; saturation drain current; silicon-on-insulator LDMOS platform technology; surface field structure; voltage -240 V; voltage -284 V; voltage 35 V to 200 V; wide-range voltage platform technology; Harmonic analysis; Imaging; Ion implantation; Layout; MOSFETs; Metals; High-voltage (HV) techniques; power MOSFETs; power semiconductor devices; silicon-on-insulator (SOI) technology;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2012.2228202