• DocumentCode
    829461
  • Title

    Value-added defect testing techniques

  • Author

    Jahangiri, Jay ; Abercrombie, David

  • Author_Institution
    Mentor Graphics Corp., Beaverton, OR, USA
  • Volume
    22
  • Issue
    3
  • fYear
    2005
  • Firstpage
    224
  • Lastpage
    231
  • Abstract
    In the transition from micrometer to nanometer technologies, many things have changed, but customer demands for low defects-per-million (DPM) failure rates have not. Modern electronic and mechanical systems contain an ever-increasing number of semiconductor components with each component containing ever-increasing gate counts per chip. With traditional quality levels, the reliability of these systems can degrade severely. Therefore, system providers must dramatically improve the reliability of each component to maintain system reliability at all levels. This article describes advanced design-for-manufacturability (DFM) test methods that target defect coverage, yield learning, and cost. The authors argue that testing can be useful for more than filtering chips. It can directly help target test pattern provide DFM tools and reduce overall costs.
  • Keywords
    automatic test pattern generation; design for manufacture; design for testability; fault diagnosis; integrated circuit testing; integrated circuit yield; logic testing; defects-per-million failure rates; design-for-manufacturability test methods; nanometer technologies; semiconductor components; system reliability; value-added defect testing techniques; Copper; Costs; Design for manufacture; Explosives; Fabrication; Fluctuations; Integrated circuit testing; Manufacturing industries; Nanoscale devices; Stress; DFM test methods; advanced design-for-manufacturability; defect testing techniques;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2005.74
  • Filename
    1438277