A 160-GHz Frequency-Translation Phase-Locked Loop With RSSI Assisted Frequency Acquisition

Author

Wei-Zen Chen ; Tai-You Lu ; Yan-Ting Wang ; Jhong-Ting Jian ; Yi-Hung Yang ; Kai-Ting Chang

Author_Institution

Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan

Volume

61

Issue

6

fYear

2014

fDate

Jun-14

Firstpage

1648

Lastpage

1655

Abstract

A 160-GHz frequency-translation PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3rd harmonic mixer incorporating a frequency tripler for frequency down conversion. A transformer-based VCO is utilized to alleviate capacitive and resistive load associated with varactor and succeeding buffer stages. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatic frequency sweeping and fast locking. Fabricated in 65 nm CMOS technology, the chip size is 0.92 mm². The PLL locking time is less than 3 μs. This chip drains 24 mW from a 1.2 V power supply.

Keywords

CMOS analogue integrated circuits; frequency multipliers; millimetre wave integrated circuits; millimetre wave mixers; millimetre wave oscillators; phase locked loops; transformers; varactors; voltage-controlled oscillators; 3rd harmonic mixer; CMOS technology; RSSI assisted frequency acquisition; automatic frequency sweeping; buffer stages; capacitive load; fast locking; frequency 156.4 GHz to 159.2 GHz; frequency 160 GHz; frequency down conversion; frequency tripler; frequency-translation PLL; phase-locked loop; power 24 mW; received signal strength indicator; resistive load; size 65 nm; transformer-based VCO; varactor; voltage 1.2 V; Harmonic analysis; Mixers; Noise; Phase locked loops; Voltage-controlled oscillators; Harmonic mixer; PLL; RSSI; tripler;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2013.2295016

Filename

6728756