Implementation of a self-timed segmented bus

We propose an asynchronous structure for implementation on a SoC. An intersegment topological arrangement preserves parallelization and, through a so-called central arbiter, efficiently organizes communication with high signaling speed in the proposed structure. Researchers proposed the concept of segmenting buses primarily for multicomputer architectures. More recent approaches address on-chip implementation of segmented buses. We present an asynchronous segmented-bus architecture targeted for the modular design of high-performance SoC applications. The structure not only enables faster operation than a conventional bus system but also offers lower power consumption per transferred data item. This is possible because segmentation is realized in such a way that the majority of data transfers in the system are intrasegment transactions on relatively short wires with low or moderate capacitive loads.