Evolution of substrate noise generation mechanisms with CMOS technology scaling

Substrate noise is a major obstacle for single-chip integration of mixed-signal systems. To reduce this problem and to assess its evolution with CMOS technology scaling, the different mechanisms that generate substrate noise and their dependencies on different parameters need to be well understood. In this paper, we show that with downscaling of the technology, substrate noise due to supply coupling becomes the dominant coupling mechanism when the chip substrate is directly biased with the digital ground. With Kelvin ground substrate biasing on the other hand, source/drain capacitive coupling becomes the dominant coupling mechanism. Further, we show that with downscaling, the peak value of the supply coupling noise component becomes more dependent on the relative ratio of the switching capacitance to the nonswitching capacitance, which is formed by the circuit decoupling and the nonswitching circuit elements, rather than the Ldi/dt noise. These insights illustrated in a quantitative framework are believed to be very useful for the systematic use of digital low-noise design techniques in future CMOS technologies.