Spur Reduction Techniques With a Switched-Capacitor Feedback Differential PLL and a DLL-Based SSCG in UHF RFID Transmitter

This paper presents a robust spur reduction technique using a switched-capacitor feedback differential phase-locked loop (PLL) and a delay-locked-loop (DLL)-based spread-spectrum clock generation in a UHF-band RF identification transmitter (TX). The proposed differential PLL is characterized by adopting a switched-capacitor common-mode feedback and distributed varactor biasing scheme to the differential charge pump and voltage-controlled oscillator designs, respectively, which results in down to 94 dBc in reference spur rejection with all digital parts off. Additionally, by adopting an 8-bit DLL and Hershey-Kiss modulated profile together, the proposed spread-spectrum clock generator shows more than 20-dB electromagnetic-interference reduction while providing up-, down-, and center-spread modes. Implemented in a 0.18m CMOS process, the proposed TX achieves <; - 80-dBc spur suppression with 25-dBm transmit power at 920 MHz, which complies with the most stringent regulatory spectral mask without a surface acoustic wave filter.