CMOS Hardness Assurance through Process Controls and Optimized Design Procedures

Total Dose Hardness Assurance for complimentary MOS integrated circuits is recognized throughout the industry as a difficult problem. Most of the hardness assurance proposals to date have included a large amount of radiation testing on a diffision lot or wafer basis to help guarantee the hardness of a small group of integrated circuits. This, in general, is very expensive, and alternate techniques must be explored. This paper discusses the use of process and device parameter controls along with optimized design procedures for radiation hardness to minimize the need for frequent radiation testing. Total dose data up to 1 × 106 Rads-Si is presented for several metal gate CMOS diffusion lots which demonstrates the reproducibility obtained when these control and design procedures are implemented.