DocumentCode
832034
Title
The dynamic reduction of fault simulation
Author
Maamari, Fadi ; Rajski, Janusz
Author_Institution
AT&T Bell Labs., Princeton, NJ, USA
Volume
12
Issue
1
fYear
1993
fDate
1/1/1993 12:00:00 AM
Firstpage
137
Lastpage
148
Abstract
Efficient strategies to perform selectively fault-free simulation, critical path tracing in fanout-free regions, and fault simulation of stem faults in a parallel pattern evaluation environment are presented and analyzed in an implementation-independent manner. The dynamic changes in the complexity of the fault simulation components as the fault simulation progresses and faults are detected are shown to be extremely significant. In particular, fault-free simulation tends quickly to become more expensive than both the critical path tracing within fanout-free regions and the explicit simulation of stem faults. In addition, the presence of redundant faults is shown to have an inhibiting effect on the reduction of the fault simulation complexity
Keywords
circuit analysis computing; digital simulation; fault location; logic CAD; critical path tracing; dynamic reduction; fanout-free regions; fault simulation; logic circuits; parallel pattern evaluation environment; redundant faults; selectively fault-free simulation; stem faults; Analytical models; Fault detection; Pattern analysis; Performance analysis; Performance evaluation;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.184850
Filename
184850
Link To Document