• DocumentCode
    832072
  • Title

    Minimizing total wire length by flipping modules

  • Author

    Chong, KyunRak ; Sahni, Sartaj

  • Author_Institution
    Dept. of Comput. Sci., Hongik Univ., Seoul, South Korea
  • Volume
    12
  • Issue
    1
  • fYear
    1993
  • fDate
    1/1/1993 12:00:00 AM
  • Firstpage
    167
  • Lastpage
    175
  • Abstract
    The problem of flipping modules about their horizontal and/or vertical axes so as to minimize the estimated total wire length is considered. Polynomial time algorithms are proposed for some classes of module layouts. Further, it is shown that a simple greedy heuristic often outperforms the neural network and simulated annealing heuristics proposed earlier for this problem
  • Keywords
    circuit layout CAD; minimisation; modules; greedy heuristic; module flipping; module layouts; polynomial time algorithms; total wire length minimisation; Computer science; Euclidean distance; Neural networks; Polynomials; Simulated annealing; Wire;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.184854
  • Filename
    184854
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=832072