DocumentCode
832877
Title
Design and VLSI implementation of a pattern classifier using pseudo 2D cellular automata
Author
Tzionas, P. ; Tsalides, Ph. ; Thanailakis, A.
Author_Institution
Dept. of Electr. Eng., Democritus Univ. of Thrace, Xanthi, Greece
Volume
139
Issue
6
fYear
1992
fDate
12/1/1992 12:00:00 AM
Firstpage
661
Lastpage
668
Abstract
The design and VLSI implementation of a pattern classifier based on pseudo 2D cellular automata (CA) is presented in this paper. Cellular automata exhibiting cyclic group structures are used to provide improved measures of the degree of similarity between patterns. The classifier operation is an adaptive process which gathers information during a training phase and uses them during the processing phase. For the VLSI implementation of the proposed pattern classifier, a 1.5 μm DLM n-well CMOS process has been used. The silicon area occupied by the chip is 5.46×5.45 mm2, and the clock frequency is 50 MHz
Keywords
CMOS integrated circuits; VLSI; adaptive systems; cellular automata; digital signal processing chips; learning systems; pattern recognition equipment; 50 MHz; VLSI implementation; adaptive process; cyclic group structures; n-well CMOS process; pattern classifier; pseudo 2D cellular automata; training phase;
fLanguage
English
Journal_Title
Circuits, Devices and Systems, IEE Proceedings G
Publisher
iet
ISSN
0956-3768
Type
jour
Filename
185017
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