DocumentCode :
833165
Title :
A reduced-delay sampled-data hold
Author :
Yekutiel, O.
Author_Institution :
Rensselaer Polytechnic Institute, Troy, NY, USA
Volume :
25
Issue :
4
fYear :
1980
fDate :
8/1/1980 12:00:00 AM
Firstpage :
847
Lastpage :
850
Abstract :
A data holding scheme whose phase delay is significantly less than that of the usual zero-order-hold is presented. Lower sampling rates may thus be used in closed-loop control applications. The improvement is achieved by means of simple additional software. A standard ZOH device is employed. Graphs of the resulting frequency response are presented. An example is included.
Keywords :
D/A converters; Digital-to-analog (D/A) conversion; Extrapolation; Linear systems, time-invariant discrete-time; Signal sampling/reconstruction; Added delay; Continuous time systems; Control systems; Digital control; Digital signal processors; Drives; Frequency; Sampling methods; Sequences; Signal sampling;
fLanguage :
English
Journal_Title :
Automatic Control, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9286
Type :
jour
DOI :
10.1109/TAC.1980.1102407
Filename :
1102407
Link To Document :
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