AMPLEX-SiCAL: a large dynamic range low-noise CMOS signal processor for silicon calorimeters

Author

Beuville, E. ; Joudon, A. ; Pascual, J. ; Grabit, R. ; Jarron, P. ; Stefanini, G. ; Buytaert, S. ; Cerri, C. ; Griffiths, J.L.

Author_Institution

CEA Saclay, Gif-sur-Yvette, France

Volume

39

Issue

4

fYear

1992

fDate

8/1/1992 12:00:00 AM

Firstpage

766

Lastpage

770

Abstract

An analog signal processor using commercial 3-μm CMOS technology has been designed and produced for the silicon luminosity calorimeter SiCAL of the ALEPH experiment. The authors present the results and the analysis of the various tests that have been performed on the circuit. This processor is a modified version of the AMPLEX integrated circuit designed for the inner silicon detector of the UA-2 experiment. The output voltage swing has been increased to more than 5.5 V are required for the large dynamic range of 1000 MIPs or 3.8 pC². A fast analog summation, based on a neural network principle called follower aggregation, computes the average input charges for triggering purposes. This chip contains 16 channels, with a charge amplifier, shaper, track-and-hold stage, multiplexer, fast analog sum, and a calibration system. The power consumption of the overall chip was 100 mW. The equivalent noise charge was less than 0.13 MIP for a 50 pF detector capacitance, and the peaking time was about 250 ns

Keywords

CMOS integrated circuits; analogue processing circuits; calibration; calorimeters; neural chips; nuclear electronics; semiconductor counters; silicon; 100 mW; 250 ns; 3 micron; 50 pF; ALEPH experiment; AMPLEX integrated circuit; AMPLEX-SiCAL; Si; UA-2 experiment; analog signal processor; average input charges; calibration system; calorimeters; charge amplifier; equivalent noise charge; fast analog sum; fast analog summation; follower aggregation; large dynamic range low-noise CMOS signal processor; modified version; multiplexer; neural network principle; output voltage swing; overall chip; peaking time; power consumption; track-and-hold stage; triggering purposes; CMOS process; CMOS technology; Circuit testing; Detectors; Dynamic range; Integrated circuit technology; Performance analysis; Signal design; Signal processing; Silicon;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.159703

Filename

159703