Calibration of parallel ΔΣ ADCs

Author

Batten, Robert D. ; Eshraghi, Aria ; Fiez, Terri S.

Author_Institution

Sch. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA

Volume

49

Issue

6

fYear

2002

fDate

6/1/2002 12:00:00 AM

Firstpage

390

Lastpage

399

Abstract

A method of calibrating the gain and offset of each channel in parallel ΔΣ analog-to-digital converters (ADCs) is presented. It uses a digital ΔΣ modulator to perform fast and simple offline calibration. Simulations performed on the converter show greater than 30-dB reduction in unwanted tones when this calibration algorithm is used on an eight-channel second-order time-interleaved parallel converter with a 1% gain mismatch and 1-mV offset mismatch. The calibration method is general and can be used with any parallel ΔΣ ADC including time-interleaved- and Hadamard-modulation-based architectures.

Keywords

analogue-digital conversion; calibration; delta-sigma modulation; parallel architectures; Hadamard modulation architecture; calibration algorithm; gain mismatch; offset mismatch; parallel sigma-delta analog-to-digital converter; time-interleaved architecture; Bandwidth; Calibration; Error correction; Error correction codes; Filters; Linearity; Parallel architectures; Quantization; Radiative recombination; Signal resolution;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/TCSII.2002.803468

Filename

1038825