Development of a CMOS time memory cell VLSI and a CAMAC module with 0.5 ns resolution

Author

Arai, Y. ; Ikeno, M. ; Matsumura, T.

Author_Institution

KEK, Nat. Lab. for High Energy Physics, Ibaraki, Japan

Volume

39

Issue

4

fYear

1992

fDate

8/1/1992 12:00:00 AM

Firstpage

784

Lastpage

788

Abstract

A CMOS time-to-digital converter chip, the time memory cell (TMC), for a high-rate wire chamber application has been developed. The chip had a timing resolution of 0.52 ns, dissipated only 7 mW/channel, and contained 4 channels in a chip. Each channel had 1024 memory locations which acted as a buffer 1 μs deep. The chip was fabricated in a 0.8-μm CMOS process and had dimensions of 5.0 mm by 5.6 mm. Using the TMC chip, a CAMAC module with 32 input channels was developed. This module was designed to operate in both common start and common stop modes. The module circuit and test results are described

Keywords

CAMAC; CMOS integrated circuits; VLSI; analogue-digital conversion; nuclear electronics; physics computing; proportional counters; 0.8 micron; 5 mm; 5.6 mm; CAMAC module; CMOS time memory cell VLSI; TMC; common start; common stop modes; high-rate wire chamber application; module circuit; test results; time memory cell; time-to-digital converter chip; timing resolution; CAMAC; CMOS process; CMOS technology; Circuit testing; Clocks; Delay effects; Energy resolution; Laboratories; Timing; Very large scale integration;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.159707

Filename

159707