Title :
Sub-threshold SRAM bit cell pnn for VDDmin and power reduction
Author :
Chien, Y.C. ; Chiang, I.H. ; Wang, J.S.
Author_Institution :
SoC/AIM-HI Center & Dept. of EE, Nat. Chung Cheng Univ., Chiayi, Taiwan
fDate :
September 25 2014
Abstract :
The bit cell is a key component that determines the VDDmin and power consumption of a sub-threshold static random access memory (SRAM). A new bit cell with a pnn-type latch structure is proposed. The analysis and measurement results indicate that the pnn bit cell outperforms the conventional bit cells in terms of VDDmin and power reduction.
Keywords :
SRAM chips; flip-flops; power consumption; PNN- type latch structure; VDDmin; bit cell; power reduction; sub-threshold SRAM;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2014.2357