Properties of CMOS devices and circuits fabricated on high-resistivity, detector-grade silicon

Author

Holland, S.

Author_Institution

Lawrence Berkeley Lab., California Univ., Berkeley, CA, USA

Volume

39

Issue

4

fYear

1992

fDate

8/1/1992 12:00:00 AM

Firstpage

809

Lastpage

813

Abstract

A CMOS process that is compatible with silicon p-i-n radiation detectors has been developed and characterized. A total of twelve mask layers were used in the process. A CMOS test chip has been designed, fabricated and tested. The test chip contained NMOS and PMOS transistors of various geometries, test structures for isolation studies, and simple circuitry. This allowed for the characterization of both the circuit performance and packing density possible with this technology. The process is described, with particular emphasis on the design and experimental results for the NMOS device. Circuit performance is presented. The results presented show that radiation detectors and CMOS electronics can be fabricated on the same substrate using a conventional CMOS process

Keywords

CMOS integrated circuits; nuclear electronics; semiconductor counters; silicon; CMOS devices; CMOS electronics; NMOS; PMOS transistors; Si; circuit performance; detector-grade; high-resistivity; isolation studies; mask layers; p-i-n radiation detectors; packing density; simple circuitry; test chip; test structures; CMOS process; CMOS technology; Circuit optimization; Circuit testing; Geometry; MOS devices; MOSFETs; PIN photodiodes; Radiation detectors; Silicon;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.159712

Filename

159712