Signed higher-radix full-adder algorithm and implementation with current-mode multi-valued logic circuits

A novel algorithm for full-addition of two signed, higher-radix numbers is proposed and implemented by combining multi-valued logic min, max, literal and cyclic operators. Owing to disjoint terms involved, multi-valued logic min and max operators are replaced with ordinary transmission operation and sum, respectively. A multi-valued logic cyclic gate is designed by using a current-mode threshold circuit while the literal is realised by only voltage-mode switching circuits. The threshold circuit employed within the cyclic gate exhibits improved dynamic behaviour compared to its previous counterparts employing voltage-mode binary logic switching circuits. It also allows much higher radices compared to previous current-mode threshold circuits owing to its superior mismatch properties. Thus, the cyclic gate achieves a superior performance compared to its predecessors. As a direct extension to cyclic operation in radix-8, a resultant single-digit, radix-8 full-adder and its 3-bit counterpart voltage-mode circuits are designed and their performance compared. It is shown that the developed signed addition algorithm can be realised by using the proposed full-adder. Finally, the algorithm is also exploited for a multi-digit case. Simulation results demonstrate that proposed architectures can be used in high-performance arithmetic units