DocumentCode
834455
Title
Junction temperature induced thermal snapback breakdown of MOSFET device
Author
Chung, Young S.
Author_Institution
SMARTMOS Technol. Center, Motorola, Tempe, AZ, USA
Volume
23
Issue
10
fYear
2002
Firstpage
615
Lastpage
617
Abstract
Continued scaling of semiconductor devices is increasingly concerned with physical limits of maximum junction temperature. This paper reports the mechanism of a junction temperature induced thermal snapback breakdown of a MOSFET device in the absence of the high electric field. The thermal snapback breakdown results from Fermi-level shift and thermally generated hole current driven by the junction temperature. It occurs before the junction temperature reaches the intrinsic level and thus determines a fundamental physical limit of MOSFET device operation.
Keywords
Fermi level; MOSFET; avalanche breakdown; semiconductor device breakdown; semiconductor device models; temperature distribution; BiCMOS technology; Fermi-level shift; MOSFET; avalanche snapback breakdown; intrinsic level; junction temperature induced thermal snapback breakdown; lateral-diffused MOS transistors; maximum junction temperature; physical limits; power density limit; semiconductor device scaling; thermally generated hole current; Density measurement; Electric breakdown; Electrothermal effects; Isothermal processes; MOSFET circuits; Power measurement; Pulse measurements; Semiconductor device breakdown; Semiconductor devices; Temperature;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2002.803762
Filename
1039185
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