Radiation Hardened CMOS/SOS Memory Circuits

Large-scale-integrated circuits which combine radiation hardness with density, high speed and low power dissipation require both hardened processes and hardened circuit design methods. CMOS/SOS circuits featuring self-compensation, self-biasing and parameter tracking accommodate a wide range of nonuniform on-chip parameter variations. These variations result from exposure to a nuclear radiation event, as well as from MOS device processing, temperature and power-supply effects. The circuits discussed in this paper are key elements for radiation-hardened memory designs [up to 106 rads(Si)] with state-of-the-art LSI density and performance. The CMOS/SOS memory cell sizes of 3.1 mil2 for a six-device, and 2.5 mil2 for a four-device, static cell are nearly five times smaller than previous radiation-hardened designs.