Demonstration of multiply-accumulate unit for programmable band-pass ADC

We describe a recent demonstration of a Multiply-Accumulate (MAC) unit, the core of digital signal processor that implements programmable band-pass signal filtering. This MAC unit can be clocked at 20 GHz and is capable of performing 2.5 billion MAC operations per second for 7-bit data samples and 16-bit filter coefficients arriving in bit-serial mode. The unit was designed using VHDL for functional verification and timing optimization and it was implemented in Northrop Grumman Space Technology´s (NGST´s) 8 kA/cm² J110E Niobium process. We also describe our design approach, which resulted in this successful demonstration, and discuss lessons learned, particularly the risks associated with fringe field magnetic coupling between bias and signal lines.