Edge Profile Effect of Tunnel Oxide on Erase Threshold-Voltage Distributions in Flash Memory Cells

Author

Kim, Bomsoo ; Kwon, Wook-Hyun ; Baek, Chang-Ki ; Son, Younghwan ; Park, Chan-Kwang ; Kim, Kinam ; Kim, Dae M.

Author_Institution

Sch. of Comput. Sci., Korea Inst. for Adv. Study, Seoul

Volume

53

Issue

12

fYear

2006

Firstpage

3012

Lastpage

3019

Abstract

The erase threshold-voltage (VT) distribution in Flash electrically erasable programmable read-only memory cells was investigated versus the tunnel oxide edge profiles in self-aligned shallow trench isolation (SA-STI) and self-aligned poly (SAP) cells. The capacitive coupling with offset voltage correction is transcribed into VT transient for simulating erase VT dispersion without numerous full structure device simulations. It is shown that SAP gives rise to smaller VT dispersion, compared with SA-STI. The VT dispersion resulting from variations in dielectric thickness and oxide edge profiles is shown to fall far short of observed VT distribution, calling for examination of additional process and cell parameters

Keywords

EPROM; coupled circuits; EEPROM; capacitive coupling equation; edge profile effect; electrically erasable programmable read-only memory cell; erase threshold voltage distributions; flash memory cells; offset voltage; self aligned shallow trench isolation; self-aligned poly cells; tunnel oxide; Dielectrics; Difference equations; Differential equations; Dispersion; EPROM; Flash memory cells; Geometry; PROM; Threshold voltage; Tunneling; Capacitive coupling equation with offset voltage; Flash electrically erasable programmable read-only memory (EEPROM) cell; edge profile effect; erase threshold voltage distribution;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2006.885101

Filename

4016346