• DocumentCode
    839948
  • Title

    Efficient algorithm for logic design using multiplexers

  • Author

    Shankar, V.S.

  • Author_Institution
    Defence Electron. Res. Lab., Hyderabad
  • Volume
    24
  • Issue
    3
  • fYear
    1988
  • fDate
    2/4/1988 12:00:00 AM
  • Firstpage
    142
  • Lastpage
    144
  • Abstract
    An algorithmic procedure has been developed for the realisation of any Boolean function F(n) of n variables with a single multiplexer of minimum size. This procedure gives the choice of control variables to be used for the realisation of the function. The algorithm is iterative in nature and very suitable for machine implementation
  • Keywords
    Boolean functions; logic design; Boolean function; algorithmic procedure; control variables; logic design; machine implementation; multiplexers;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • Filename
    191591
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=839948