Testing On-Die Process Variation in Nanometer VLSI

As device technology progresses toward 45 nm and beyond, the fidelity of process parameter modeling becomes questionable. The authors propose the concept of process variation (PV) testing, which involves applying an innovative fault model and test methodology that uses PV sensing circuitry and frequency domain analysis. Rather than pinpointing the variation of different parameters, the architecture proposed by the authors looks at the effect of PV on a chip indirectly and collectively. The novelty of this architecture is in shifting the strategy of VLSI testing to the frequency domain by using a distributed network of frequency-sensitive sensors such as ring oscillators. This provides an intrinsic advantage by minimizing the effect of noise (signal integrity loss, crosstalk, IR drop, and so on) and by using the powerful concept of digital signal processing for test analysis. The test architecture does not interfere with the rest of the circuit, thus providing freedom to tune the accuracy of PV test by choosing the proper number and type of oscillators.