DocumentCode :
840649
Title :
Integrating Phase-Change Memory Cell With Ge Nanowire Diode for Crosspoint Memory—Experimental Demonstration and Analysis
Author :
Kim, SangBum ; Zhang, Yuan ; McVittie, James P. ; Jagannathan, Hemanth ; Nishi, Yoshio ; Wong, H. S Philip
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., Stanford, CA
Volume :
55
Issue :
9
fYear :
2008
Firstpage :
2307
Lastpage :
2313
Abstract :
In this paper, we demonstrate a novel phase-change memory cell utilizing a low-temperature in situ doped single crystalline germanium nanowire diode as a bottom electrode as well as a memory-cell selection device. The integrated memory cell shows promising characteristics such as low programming current, large set/reset resistance ratio, and rectifying behavior, which is required for high-density 3-D crosspoint memory. The small contact area determined by the diameter of nanowires enables low programming current below 200 for reset and 50 for set. The average resistance ratio of set/reset state programmed by repetitive pulse programming is 82, which is large enough for large-array operation. The heterojunction formed between in situ doped Ge nanowires and Si substrate provides isolation for crosspoint-memory operation.
Keywords :
electric resistance; elemental semiconductors; germanium; nanowires; semiconductor diodes; semiconductor heterojunctions; semiconductor storage; Ge; Si; bottom electrode; doped single crystalline germanium nanowire diode; heterojunction; high-density 3-D crosspoint memory; integrated memory cell; large-array operation; memory-cell selection device; phase-change memory cell; programming current; rectifying behavior; repetitive pulse programming; set-reset resistance ratio; Crystallization; Current density; Germanium; Nanoscale devices; Nonvolatile memory; Phase change materials; Phase change memory; Semiconductor diodes; Stacking; Temperature; Crosspoint memory; nanowire diode; ovonic unified memory (OUM); phase-change memory (PCM); phase-change random-access memory (PRAM); vapor–liquid–solid (VLS) technique;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2008.927631
Filename :
4603170
Link To Document :
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