Title :
The Grand Pareto: A Methodology for Identifying and Quantifying Yield Detractors in Volume Semiconductor Manufacturing
Author :
Desineni, Rao ; Berndlmaier, Zachary ; Winslow, Jonathan ; Blauberg, Alisa ; Chu, Benjamin R.
Author_Institution :
IBM Corp., Hopewell Junction, NY
fDate :
5/1/2007 12:00:00 AM
Abstract :
A method of communicating a unified pareto, we call "Grand Pareto," for technology-wide failure mechanisms that limit the profitability of a fabrication facility is presented. The Grand Pareto leverages multiple defect detection and isolation techniques in conjunction with state-of-the-art physical failure analysis and statistical yield analysis techniques to create a single message for the process community to drive the yield improvement efforts. The methodology has been successfully deployed at IBM where it has been assisting identification of key yield detractors for several high-end microprocessors in volume production
Keywords :
Pareto analysis; failure analysis; fault diagnosis; integrated circuit yield; isolation technology; Grand Pareto method; fabrication facility; high-end microprocessors; isolation techniques; multiple defect detection; physical failure analysis; semiconductor manufacturing; statistical yield analysis techniques; technology-wide failure mechanisms; yield detractors; Fabrication; Failure analysis; Inspection; Isolation technology; Manufacturing; Production facilities; Profitability; Semiconductor device manufacture; Systematics; Testing; Defect pareto; diagnosis; failure analysis; yield enhancement; yield learning;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
DOI :
10.1109/TSM.2007.896641
