DocumentCode :
84146
Title :
Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices
Author :
Ziabari, Amirkoushyar ; Je-Hyoung Park ; Ardestani, Ehsan K. ; Renau, Jose ; Sung-Mo Kang ; Shakouri, Ali
Author_Institution :
Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Volume :
22
Issue :
11
fYear :
2014
fDate :
Nov. 2014
Firstpage :
2366
Lastpage :
2379
Abstract :
High-temperature and temperature nonuniformity in high-performance integrated circuits (ICs) can significantly degrade chip performance and reliability. Thus, accurate temperature information is a critical factor in chip design and verification. Conventional volume grid-based techniques, such as finite-difference and finite-element methods (FEMs), are computationally expensive. In an effort to reduce the computation time, we have developed a new method, called power blurring (PB), for calculating temperature distributions using a matrix convolution technique in analogy with image blurring. The PB method considers the finite size and boundaries of the chip as well as 3-D heat spreading in the heat sink. PB is applicable to both static and transient thermal simulations. Comparative studies with a commercial FEM tool show that the PB method is accurate within 2%, with orders of magnitude speedup compared with FEM methods. PB can be applied to very fine power maps with a grid size as small as 10 μm for a fully packaged IC or submicrometer heat sources in power electronic transistor arrays. In comparison with architecture-level thermal simulators, such as HotSpot, PB provides much more accurate temperature profiles with reduced computation time.
Keywords :
convolution; finite element analysis; heat sinks; integrated circuit design; integrated circuit packaging; integrated circuit reliability; matrix algebra; temperature distribution; thermal analysis; transient analysis; 3D heat spreading; HotSpot; ICs; PB method; architecture-level thermal simulators; chip design; chip performance degradation; chip verification; commercial FEM tool; fast static thermal analysis method; finite-difference methods; finite-element methods; heat sink; high-performance integrated circuits; image blurring; matrix convolution technique; packaged integrated circuits; power blurring; power devices; power electronic transistor arrays; power maps; reliability; submicrometer heat sources; temperature distributions; temperature information; temperature nonuniformity; transient thermal analysis method; transient thermal simulations; volume grid-based techniques; Geometry; Heat sinks; Heating; Integrated circuits; Silicon; Temperature distribution; Thermal analysis; Finite-element method (FEM); heat transfer; integrated circuits (ICs); package; power electronics; temperature; thermal management; thermal simulation; thermal simulation.;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2013.2293422
Filename :
6729105
Link To Document :
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