Title :
Parallel processing for Viterbi algorithm
Author :
Kuei Ann Wen ; Jau Yien Lee
Author_Institution :
Inst. of Electr. & Comput. Eng., Nat. Cheng Kung Univ., Tainan
fDate :
8/18/1988 12:00:00 AM
Abstract :
Dual-dimensional parallelisation for the Viterbi algorithm is exploited. That is, parallelisation of the decoding procedures within each stage of the trellis and parallelisation of the decoding procedures are expanded to consecutive stages without excessive path memories. Since an arbitrary number of stages can be parallelised, the trade-off between computation speed and degree of integration can be adjusted as required
Keywords :
VLSI; cellular arrays; decoding; microcomputer applications; parallel architectures; parallel processing; 2D parallel processing; VLSI systolic arrays; Viterbi algorithm; Viterbi decoding; arbitrary number of stages; computation speed; decoding procedures; degree of integration; expanded to consecutive stages; trade-off; trellis search parallelism;
Journal_Title :
Electronics Letters
