• DocumentCode
    842449
  • Title

    Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers

  • Author

    Ahmed, Nova ; Tehranipoor, Mohammad ; Ravikumar, C.P. ; Butler, Kenneth M.

  • Volume
    26
  • Issue
    5
  • fYear
    2007
  • fDate
    5/1/2007 12:00:00 AM
  • Firstpage
    896
  • Lastpage
    906
  • Abstract
    At-speed testing is becoming crucial for modern very-large-scale-integration systems, which operate at clock speeds of hundreds of megahertz. In a scan-based test methodology, it is common to use a transition delay fault model for at-speed testing. The launching of the transition can be done either in the last cycle of scan shift [launch-off-shift (LOS)], or in a functional launch cycle that follows the scan shift and precedes the fast capture [launch-off-capture (LOC)]. The LOS technique offers significant advantages over the LOC in terms of coverage and pattern count, but since it requires the scan enable (SEN) signal to change state in the time period of one functional clock cycle, considerable engineering resources are required to close the timing on the SEN signal. Low-cost testers will not be able to provide the at-speed SEN signal as required by the LOS technique. We propose a scan-based at-speed methodology that generates "local" SEN signals that are guaranteed to switch in one functional clock cycle even when the external SEN signal does not change state at functional speed. Our technique is based on encapsulating the SEN control signal in the scan test data. A new scan cell, which is called the last transition generator, must be inserted in every scan chain for generating internal SEN signals. The proposed method is robust, practical, and readily implemented using commercial tools available today
  • Keywords
    VLSI; fault diagnosis; integrated circuit testing; LOC; LOS; SEN; launch-off-capture; launch-off-shift; low cost tester; low cost testers; scan enable generation; scan enable signal; transition fault testing; Circuit faults; Circuit testing; Clocks; Delay; Instruments; Lab-on-a-chip; Robustness; Signal generators; Switches; System testing; Launch-off-capture (LOC); launch-off-shift (LOS); low-cost tester; scan enable signal (SEN); transition delay fault testing;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2006.884405
  • Filename
    4193566