A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS

An 18-Mb full ternary CAM with low-voltage matchline sensing scheme (LVMLSS) is designed and fabricated in 65-nm bulk CMOS process. LVMLSS has three key techniques: voltage down converter, differential sense amplifier with matchline isolation, and reference voltage generation scheme. With these techniques, LVMLSS can reduce the dynamic power consumption of matchlines to 33% compared with conventional one and realizes 42% fast match-line sensing. At 1.0-V typical supply voltage, 250-MHz search frequency is achieved. The power consumption of fully paralleled search operation at 250 MHz is 9.3 W, which is 66% smaller than previous work. This work has realized high-speed, low-power, and robust large-scale TCAM. We believe that this work will greatly contribute to reducing the power of network systems.