Symmetric and Asymmetric Design and Implementation of New Cascaded Multilevel Inverter Topology

Nowadays, use of multilevel inverters in high-power applications clearly can be seen. High quality and lower distortion of the output voltage and low blocking voltage of semiconductor switches are being presented as the major privileges of the multilevel inverter compared to the traditional voltage source inverter. In this paper, a new topology of multilevel inverter is proposed as fundamental block. The proposed topology is generalized using series connection of the fundamental blocks. The proposed multilevel inverter has been analyzed in both symmetric and asymmetric operation modes. A great perfection in voltage levels number with minimum switching devices has been obtained in both symmetric and asymmetric modes. Thereafter, a detailed study of losses and peak inverse voltage (PIV) of the proposed multilevel inverter is given. Also, in continuation, a comparison between the proposed topology and the traditional one and a recently developed topology is carried out. Finally, a computer simulation using MATLAB/Simulink is presented and a laboratory prototype implementation verifies the results.