VLSI implementation of a maximum-likelihood decoder for the Golay (24, 12) code

Author

Abbaszadeh, Ayyoob D. ; Rushforth, Craig K.

Author_Institution

Dept. of Electr. Eng., Utah Univ., Salt Lake City, UT, USA

Volume

6

Issue

3

fYear

1988

fDate

4/1/1988 12:00:00 AM

Firstpage

558

Lastpage

565

Abstract

J.H. Conway and N.J.A. Sloane (1986) have introduced an algorithm for the exact maximum-likelihood decoding of the Golay (24, 12) code in the additive white Gaussian noise channel that requires significantly fewer computations than previous algorithms. An efficient bit-serial VLSI implementation of this algorithm is described. The design consists of two chips developed using path-programmable logic (PPL) and an associated system of automated design tools for three-μm NMOS technology. It is estimated that this decoder will produce an information bit every 1.6-2.4 μs. Higher speeds can be achieved by using a faster technology or by replicating the chips to perform more operations in parallel

Keywords

CAD; VLSI; codes; decoding; electronic engineering computing; field effect integrated circuits; white noise; 1.6 to 2.4 mus; Golay code; NMOS technology; additive white Gaussian noise channel; automated design tools; bit-serial VLSI implementation; maximum-likelihood decoder; path-programmable logic; Additive white noise; Binary codes; Euclidean distance; Linear code; Logic design; MOS devices; Maximum likelihood decoding; Maximum likelihood estimation; Vectors; Very large scale integration;

fLanguage

English

Journal_Title

Selected Areas in Communications, IEEE Journal on

Publisher

ieee

ISSN

0733-8716

Type

jour

DOI

10.1109/49.1924

Filename

1924