A parallel A/D converter array structure with common reference processing unit

A successive-approximation A/D converter array with a parallel architecture is proposed. The circuit is realized using a switched-capacitor (SC) technique. The architecture of the array is based on a common-reference processing unit and multichannel parallel-input, signal processing units. The latter, which are the main part of the array, are insensitive to the capacitor ratio mismatch and the gain of the amplifiers. The linearity of the array is insensitive to parasitic capacitors and offset of the amplifiers. The conversion time is linearly proportional to the number of bits required. Due to the small number of components needed and the simplicity of the circuit realization, the proposed A/D solution is suitable for VLSI implementation. A typical application would be in a small sensor system, where a sensor array, parallel A/D converters, and parallel digital processors are integrated in a single chip