100 Mbit/s adaptive data compressor design using selectively shiftable content-addressable memory

A hardware architecture for an adaptive lossless data compressor is described. The architecture is suitable for implementation on a single ASIC. The architecture results from an investigation aimed at developing novel compression algorithms that can utilise the fine-grain parallel processing capabilities of VLSI integrable structures and hence, achieve high performance. The efficiency of different hardware structures are assessed for text, image and machine code data compression through simulation. Suitable candidate designs based around a shifting content-addressable memory (CAM) array are identified. A design for one such option is developed using a commercial CAD package. Despite using modest 2 μm CMOS technology, compressed data is produced at a minimum rate of 100 Mbit/s. Details of the design are presented